Artículo wiki · Colección 08
STM32
Referencia técnica sobre STM32 para el diseño, integración e implementación de sistemas de energía inalámbrica.
STMicroelectronics STM32 lines appear frequently in SiCore embedded reference hardware because of integrated motor-control peripherals ( HRTIM, advanced timers ), rich analog ( ADC with injection and oversampling ), and mature STM32Cube ecosystem. Family choice tracks power level and connectivity: STM32G4 for compact receiver inverters, STM32H7 for multi-channel dock controllers with Ethernet, STM32L4 where receiver standby current must stay below milliamps between charge sessions.
CubeMX and CubeIDE accelerate pinmux and clock tree setup, but production firmware treats generated initialization as bootstrap only — control loops and safety paths are hand-audited and version-controlled separately.
01Family mapping
- STM32G4: primary choice for 3–10 kW receivers — HRTIM, FMAC, CORDIC accelerators for resonant control.
- STM32H7: dock transmitters needing dual CAN-FD, Ethernet, and multi-ADC synchronized sampling.
- STM32L4/L5: telemetry nodes and low-power alignment sense subsystems on battery-backed receivers.
- STM32F3 legacy: fielded pads still on F3; migration plans maintain pin-compatible upgrade paths where possible.
02Peripheral configuration patterns
Center-aligned PWM from HRTIM or TIM1/TIM8 feeds gate drivers with hardware dead-time and break inputs tied to comparator outputs from over-current sense. ADC injected sequences trigger mid-PWM for synchronous sampling of primary current and DC bus voltage. DMA circular mode streams samples to RAM buffers consumed by RTOS control tasks at 10–20 kHz while protection comparators act in hardware within nanoseconds.
SiCore STM32 BSP enforces consistent naming for HAL callbacks vs RTOS primitives — timer update ISRs release semaphores; heavy math never runs inside HAL weak callbacks unmodified.
03Production and maintenance
Unique device ID and flash option bytes support read-out protection tiers for IP protection without blocking field OTA. ST’s longevity program parts are specified in SiCore BOMs with explicit PCN review. When ST releases errata affecting ADC sync or HRTIM behavior, SiCore publishes minimum HAL pack versions and regression test scope for affected pad and receiver SKUs.
