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Lista de Verificación de Electrónica de Potencia

Referencia técnica sobre Lista de Verificación de Electrónica de Potencia para el diseño, integración e implementación de sistemas de energía inalámbrica.

6 minArtículo 50/50Electrónica de Potencia

Power Electronics Checklist — educational diagram — Fig.: Diagrama educativo de “Power Electronics Checklist”.

Use a structured checklist so dock and vehicle power stages do not ship with gaps in protection, EMC, or thermal margin. The list below summarizes classic gate items for AGV/AMR wireless power programs — adapt to your voltage class and regional codes.

01Design phase

Topology and device selection documented with loss budget across alignment window.
DC bus, pre-charge, discharge, and fuse coordination defined.
Gate drive, dead time, and shoot-through protection verified on worst spread samples.
Current and voltage sense placement validated for control and protection bandwidth.

Power Electronics Checklist — supporting diagram — Fig.: Ilustración de apoyo para “Power Electronics Checklist”.

02Validation phase

Efficiency map at min, nominal, max coupling and temperature corners.
EMC pre-compliance and immunity per install class.
Thermal soak at nameplate duty inside final enclosure.
Fault matrix: OC, OV, OT, grid loss, comm loss, misalignment, foreign object if applicable.

03Production and field

Production test limits for key waveforms or power metrics. Service documentation for bus discharge, filter replacement, and firmware safe states. Fleet logging of faults tied to dock ID and alignment statistics for continuous improvement.

04Sign-off

Cross-functional review: power, magnetics, firmware, safety, manufacturing.
Change control for any post-qualification BOM or layout edit.
Spares and obsolescence plan for semiconductors on multi-year AMR contracts.