Protección contra Sobrecorriente

Overcurrent protection limits conductor and semiconductor stress when load impedance drops below design expectation — from receiver misalignment causing reflected power, to shorted output stages, to foreign objects presenting low-resistance paths across the coupling gap. SiCore dock inverters deliver 80–150 A equivalent secondary current at full power; receiver synchronous rectifiers switch comparable currents with minimal ON-state margin before thermal destruction in microseconds without protection.

Protection must coordinate across the power path: AC mains breaker, DC bus fuse or electronic limit, inverter peak current detect, and receiver output fuse or BMS disconnect — each layer responds at appropriate speed without nuisance tripping during normal soft-start, alignment search, or brief inrush.

01Detection methods

• Shunt and Hall-effect sensing: primary-side input current and secondary-reflected current monitoring with calibrated ADC and hardware comparators.
• Desaturation detection: IGBT and high-voltage FET fault sensing for short-circuit events faster than current loop bandwidth.
• Cycle-by-cycle limiting: PWM truncation when instantaneous current exceeds threshold — preserves bridge during transient overload.
• Receiver SR protection: per-leg current sense with latch-off on shoot-through or overload before inductor saturation.
• Coordination timers: distinguish millisecond inrush from sustained fault before latching shutdown and requiring reset.

02Dock and receiver implementation

SiCore inverter firmware implements tiered response: current limit reduces power gracefully during moderate overload; hard fault disables gate drivers within microseconds on comparator trip. Multi-pad sites evaluate parallel fault contribution — one pad's fault must not propagate excessive current through shared DC bus or facility neutral. Receiver output protection interfaces with customer BMS — SiCore specifies maximum fault current and clearing time so BMS contactors and fuses coordinate without welding or nuisance fleet downtime.

Misalignment and partial FOD conditions can elevate primary current without obvious short — overcurrent logic integrates with power control and FOD to distinguish benign reflected power from hazardous fault. Calibration accounts for temperature drift in shunt amplifiers and Hall sensors across −20 °C to +50 °C dock pit ambient.

03Validation and field behavior

Protection validation includes simulated output short, primary-side fault injection, and concurrent charge with minimum battery impedance. Nuisance trip rate is monitored in fleet telemetry — excessive trips trigger review of threshold margin, alignment tolerance, or site-specific load conditions. Service documentation identifies reset procedures after latched overcurrent events and prohibits bypass of protection components during troubleshooting.