SiCore Dynamics

Wiki article · Collection 08

PWM

Engineering reference on PWM for wireless power system design, integration, and deployment.

6 minArticle 08/13Embedded
PWM — educational diagram
Fig.: Educational diagram for “PWM”.

PWM is the primary actuation mechanism for wireless power inverters and active rectifiers on AGV receivers. SiCore firmware configures advanced timers or HRTIM modules to generate complementary half-bridge drives with programmable dead-time, idle states, and fault break inputs that force safe gate-off patterns faster than software intervention.

Modulation strategy varies by topology: fixed-frequency phase shift for some resonant links, frequency dither for soft switching maintenance, or hybrid duty-plus-phase on multi-phase dock arrays feeding large AGV pads.

01Configuration essentials

  • Center-aligned PWM for symmetric ripple and cleaner ADC sampling windows.
  • Dead-time insertion: 200–800 ns typical depending on MOSFET/SiC device and gate driver.
  • Break inputs: tie comparator OCP and external ESTOP to timer MOE disable with defined idle polarity.
  • Synchronization: phase lock multiple timer instances for multi-coil dock transmitters.
  • Minimum pulse width: enforce in hardware and software to prevent shoot-through at duty extremes.
PWM — supporting diagram
Fig.: Supporting illustration for “PWM”.

02Control modes

Duty cycle modulation regulates bus current on non-resonant stages; phase shift between half-bridge legs controls power in series-resonant WPT links without violating ZVS constraints over load range. SiCore control tasks update compare registers via buffer shadow loads at period boundaries to prevent glitches. Synchronous rectifier PWM on the receiver side tracks primary phase with alignment compensation derived from secondary current zero-cross detection.

Light-load operation may enter burst mode or frequency foldback — algorithms document audible noise and EMI implications for warehouse deployment near acoustic-sensitive zones.

03Validation

Gate waveform capture on scope confirms dead-time, rise/fall, and break response latency. Firmware regression tests assert compare register clamping when BMS requests zero current mid-session. EMC pre-compliance correlates PWM frequency plans with conducted emissions peaks; optional spread-spectrum is gated behind config because it interacts with resonant tuning stability.