Wiki article · Collection 08

RTOS

Engineering reference on RTOS for wireless power system design, integration, and deployment.

6 minArticle 05/13Embedded

RTOS — educational diagram — Fig.: Educational diagram for “RTOS”.

Bare-metal superloops cannot safely host modern wireless charging firmware: concurrent CAN-FD to BMS, Modbus or Ethernet to fleet gateways, logging, OTA download, and multiple closed-loop controllers require structured preemption and bounded blocking. SiCore embedded stacks use FreeRTOS or vendor-safe variants on Cortex-M4/M33/H7 with a strict split between hard real-time ISR paths and soft real-time tasks.

RTOS adoption is not universal on the smallest receivers — ultra-compact SKUs may run a cooperative scheduler — but any design with OTA and live diagnostics assumes preemptive multitasking.

01Task architecture

Highest priority (non-RTOS): PWM fault, comparator trip, and comm-loss hardware shutdown — never waits on mutex.
Control task: 1–5 kHz loop for current/power regulation, resonant tuning, and thermal derating.
Protocol tasks: CANopen or custom BMS DBC parsing, fleet telemetry, pad session state machine.
Background: flash wear-leveled logging, OTA image verify, non-critical diagnostics upload.
Idle hook: stack watermark check, watchdog service in approved task context only.

RTOS — supporting diagram — Fig.: Supporting illustration for “RTOS”.

02Synchronization discipline

Shared ADC buffers use lock-free single-producer single-consumer indices or RTOS message buffers with fixed-size structs — never unbounded queues for control data. Mutexes protecting configuration structs use priority inheritance and short hold times; control tasks never block on flash erase. Software timers drive session timeouts and alignment debounce; they do not replace hardware watchdogs for safety shutdown.

SiCore coding standards forbid malloc in runtime paths; static allocation and memory pools sized at compile time from worst-case concurrent session counts.

03Validation and debugging

Runtime stats (uxTaskGetStackHighWaterMark, cycle counters) are logged at end of commissioning and after OTA. Tracealyzer or SystemView captures are mandatory for new task layouts before SIL or CE evidence collection. Kernel tick rate is chosen to avoid beating against PWM periods — often 1 kHz tick with high-resolution timers for protocol timeouts.