PCB Layout for Power

PCB layout determines parasitic inductance and resistance that schematics ignore. At WPT frequencies, a few nanohenries in the switch loop changes overshoot, EMI, and measured efficiency. Receiver boards under AMR bellies have size constraints — every millimeter of loop area counts.

Layout is not artwork routing — it is part of the power circuit.

01Priorities

• Minimize switch loop: FET, bus cap, tank connection on one copper layer pair.
• Heavy copper or bus bars for high current paths; many vias for current sharing.
• Kelvin sense connections off main current path for control and protection.

02Isolation and clearance

Creepage and clearance for safety isolation barriers. Slotting under isolation partitions. Keep high dV/dt nodes away from sensitive analog and communication traces — use shields or cuts in planes.

03Manufacturing

• Panelization that does not weaken high-current copper.
• Solder mask defined pads versus copper defined — specify for high current.
• Revision control on copper pour changes — they are electrical changes.